Compiling Regular Computations to Fine-Grained Linear Processor Arrays

Fine-grained linear processor arrays are an important class of architectures for obtaining high performance on computationally intensive algorithms with large data sets, as found prevalently in digital signal processing and scientiic computing. The vast number of processing elements on these architectures provides a immense amount of potential parallelism but at the price of limited interconnect and ne-granularity, resulting in complex constraints on synthesis. In an attempt to overcome such restrictions, compilers must search for both iteration-level and instruction-level parallelism. This paper evaluates the iteration-level scheduling techniques of space-time mapping and loop transformation theory, and the instruction-level techniques of software pipelining and trace scheduling. In particular, the applicability of each technique to linear ne-grained processor arrays is discussed. The conclusion is that a combination of loop transformation theory, software pipelining, and space-time mapping provides a potentially powerful method for scheduling to this class of architectures.